It is known that for achieving power management in system-architectures in chips such as RF integrated chips, there are certain users that prefer to use the internal regulator mode while other users prefer to use an external regulator mode. When the RF chip is driven from an external source, the internal regulator should be switched off to avoid any current-overhead, and its output should be high-Z to ensure a no-racing condition between the internal and external regulators. This can be done if the internal regulator is disabled completely with minimum or zero quiescent current.
It is desirable to have a signal which can configure the chip into an “internal regulator” or “external regulator” mode. It is also desirable to have a “High Z” capability on the output in the internal regulator during OFF condition. Situations which need to be avoided include a race-condition at the regulator output during power up in an external regulator mode, and a high-current-state which may cause electro migration or other reliability issues every time the chip powers up, or even during operating conditions. It would be desirable if the chip could distinguish in a simple manner as to which mode it is in, i.e., external regulator mode, internal regulator mode and digital test mode
Existing Solutions and Associated Problems
One prior art method is to use software which indicates that the system is in an external regulator mode. However, the software for this purpose will generally work only after the chip wakes up. During wake up of the chip, there is a contention when the internal regulator is forced to be turned on while the external regulator is driving its output. Software can provide the required solution only to regulators that are not involved in power-up of the chip. Where software is used, the above method is not a preferred option since the software might need to be different for different customers owing to differences in their respective board configurations.
A second option is to use a dedicated IO pin in the chip. This IO cannot however be reused (INPUT/OUTPUT type). It is to be noted that this is an expensive solution particularly if the chip is IO limited.
A third option is to use an internal comparator which when driven from an external source, detects the internal and external configuration modes. In such case, the internal regulator output should be high “Z” to ensure that it does not draw current from the external regulator. Also the chip during “regulator OFF” condition has to contend with unknown voltage at the regulator output when the chip wakes up with “internal regulator mode”. In this option however, the disadvantage is that the comparator scheme will falsely detect such conditions as “external regulator mode”. It assumes a low impedance to ground when the output of any regulator is disabled. A typical prior art arrangement reflecting such a situation may be found in U.S. Pat. No. 7,013,396.
A fourth option is to use a series connected switch in the power path to avoid a race condition. However, this arrangement compromises voltage regulation as the load current passes though the switch which essentially has series switch resistance. Also, there is a need for a voltage detection mechanism which is not part of the prior art and assumes a low impedance to ground from the output of the different supplies. A typical prior art arrangement reflecting such a situation may be found in U.S. Pat. No. 4,843,224.